А вообще откуда взялся DAC: 3PD5651E, с сайта производителя или кто то разглядел на своём устройстве? По фото выложенных здесь виден только производитель.
а это я расследование проводил)
полез на сайт 3PEAK и смотрел, там в каталоге в принципе, в таком корпусе ИСКЛЮЧИТЕЛЬНО 10 битные DAC
они вообще не делают 12-битных ЦАПов
http://www.3peakic.com.cn/En/product/productes/catid/147.html
кстати!
DAC902 - Reference - 1.24V
3PD5651E - Reference - 1.1V
гммм.... обратил вот щас внимание. мот в этом вся херня моя, шум этот
В даташите 902 мелькал Rset 2кОм. А на плате какой стоит?
The full-scale output current is determined by the ratio of
the internal reference voltage (1.24V) and an external
resistor, RSET. The resulting IREF is internally multiplied by
a factor of 32 to produce an effective DAC output current
that can range from 2mA to 20mA, depending on the value of RSET.
IOUTFS = 32 • IREF = 32 • VREF/RSET
Что вы на сайте смотрели я помню, но кто то ещё подтвердил что 3PD5651E, правда не понятно откуда взято подтверждение.
Вот текст с форума:
Did a brief test. Near zero, I can distinguish quantization steps of roughly 1.5mV at the output, so IMO it is 12 bit.
Given a DAC range utilization of about 90% (some headroom for gain/offset calibration), 5Vpp AWG output voltage and 12 bits, one LSB step calculates to about 1.36mV. For 10 bits, the resolution would be only 5.43mV. How could I measure a resolution of better than 1.5mV at the output if it were only a 10-bit DAC? I have absolutely no doubts that at least the DAC in my genuine 2D72 does resolve 12 bits.
[ I do not trust the fractional millivolts displayed by my DMM, but it still can clearly distinguish ~5.5mV steps from ~1.5mV steps in its 200mV range. On my other scope @ 2mV/div I can clearly distinguish these magnitues as well, despite 500uVpp noise. ]
EDIT:
For better accurracy measured once again with scope, now using 64x averaging acquisition, and let the scope display the avg voltage along the timeline. One of the DAC steps reads 5.00mV, and the subsequent one 6.37 mV. The difference is pretty close now to the calculated 1.36mV.
Btw, there is one observable similarity to the specs of the 3PD5651E:
The voltage at Rset measures 1.11V. The 3PD5651E has a specified internal reference voltage of 1.1V, while DAC902 has 1.24V.
But there is also a difference to both, 3PD5651E and DAC902:
Both were supposed to output the reference voltage at pin 17, but there is no voltage on pin 17.
The required minimum setup and hold times of 2ns+1.5ns given in the 3PD5651E datasheet were IMO too large for 250MSPS operation either -- this would leave ony a window of 500ps where the data are allowed to change - I doubt that the FPGA can fulfill this. Even the typical setup and hold times given in the DAC902 datasheet of 1ns+1.5ns are already pretty tight, but would at least grant a window of 1.5ns for the data to change (but still challenging). Well, maybe this is even the cause for one of the nasty problems with this AWG. I have some evidence that the origin of the spikes/glitches might be on the digital side of the DAC, but not sufficient evidence to prove or disprove it (don't have fast enough equipment to measure the timing on the DAC inputs and clock).
